Well, they were innovations once. But does Intel go too far with its Terascale claims?

28 February 2007

The talk of dishonesty in PR reminded me of a bit of news from Intel earlier in February and how you really need to fact-check every little detail in the information provided by a company. At the International Solid-State Circuits Conference (ISSCC), Intel described how its research team developed a chip with 80 floating-point processors on it.

It has good headline performance, as long as you like your floating-point problems to be small, about 3Kbyte small. And it has some neat design techniques behind it, as described in the paper from the digest helpfully uploaded by PC Perspective. I would point people to the IEEE Member Digital Library but, seeing as the institution takes its own sweet time to put the proceedings online, this is the only place you can see this paper (as far as I can tell) right now.

However, what amused me was the list of 'innovations' in the device put together by the PR team at Intel.

"Intel’s Teraflops Research Chip implements several innovations for multi-core architectures:

Rapid design - The tiled-design approach allows designers to use smaller cores that can easily be repeated across the chip. A single-core chip of this size (100 million transistors) would take roughly twice as long and twice as many people to design.

Network on a chip - In addition to the compute element, each core contains a 5-port messaging passing router. These are connected in a 2D mesh network that implement message-passing. This mesh interconnect scheme could prove much more scalable than today’s multi-core chip interconnects, allowing for better communications between the cores and delivering more processor performance.

Fine-grain power management - The individual compute engines and data routers in each core can be activated or put to sleep based on the performance required by the application a person is running. In addition, new circuit techniques give the chip world-class power efficiency—1 teraflops requires only 62W, comparable to desktop processors sold today.

And other innovations - Such as sleep transistors, mesochronous clocking, and clock gating."

That's all well and good but most of these aren't actually Intel innovations. Some of them aren't even all that new. However, the reader could be expected to assume that these techniques were developed by the company based on that wording. This guy seemed to think so: as he writes "Intel calls it mesochronous clocking". Not quite. That name came from somewhere else.

Mesochronous clocking has been around for a while. It first appeared in an experimental chip put together by MIT and BBN, although they didn't give the technique its name. It was actually David Messerschmitt of the Berkeley Wireless Research Center who came up the tag 'mesochronous' in 1990.. It's basically a halfway house between synchronous and the kind of asynchronous design favoured by Steve Furber's group at the University of Manchester. The idea is that, at several gigahertz, the delay to the clock signal across a chip becomes acceptable. With mesochronous clocking you don't bother trying to distribute the same clock signal across the chip, only across tiny islands the size of an individual processor. You then use asynchronous techniques to join up the islands.

Similarly clock gating started elsewhere: the earliest mention I can find is, once again, from work at Berkeley by Bob Brodersen and his team. It's now pretty much standard in system-on-chip (SoCs) designs. It's worth noting that Brodersen is arguably the biggest evangelist for the kind of sea-of-processors approach to design exemplified by the Terascale processor - but he's been evangelising it for a good few years.

Sleep transistors are relatively new to commercial chips, but they are commonplace in 65nm designs (of which the Terascale chip is one) where leakage power is a major problem. The people behind this trick were working at NTT in 1995 when they proposed it. It's now so widespread that design-automation companies are currently slugging it out over a standard way to tell their tools where these transistors are in a design. Without that information, things can go badly wrong. Curiously, the thing that people associate with Intel for power saving - body biasing - is mentioned by the researchers but not this PR brief.

Tiled design? The marketplace is littered with the corpses of companies that whacked tens of identical processing elements on a chip, hooked them up with some form of mesh and called the result a configurable computer. Some companies are still in business doing this stuff - I am sure they either laughed their heads off or sat fuming as Intel claimed this approach to design as its own.

The things that Intel did develop, the PR brief tends to skip over. I would imagine that's because the new bits described at ISSCC were in the detail of the implementation of the floating-point engine and the wormhole router and, therefore, a tad tricky to get across to the layman.

I'll leave it to you to judge whether this was an acceptable sleight of hand on Intel's part or something that companies like this should avoid. There is also the question of how old a technology can be before you stop referring to it as an innovation just because it's the first time you used it.