Hwang's costly law

25 October 2007

Samsung is trying hard to push the idea of Hwang's Law, as seen in the company's latest move to show off an experimental 64Gbit device. In 2002, the head of the Korean company's chip business Hwang Chang-gyu gave a speech at one of the chipmaking industry's biggest technical conferences, ISSCC. There, he claimed that flash memories would break away from the prevailing trend in the chip industry and double in size every year. That was something that happened only in the very early days of the business, at the point when Gordon Moore was putting together the graph that became Moore's Law.

For much of its history, the growth in the number of functions that you can get onto one chip has wobbled between a doubling every 18 months or two years. And a lot depends on how you measure the number of functions – something that Intel has made use of on several occasions. Right now, the rate seems to be a doubling every two years, which fits neatly with Intel's own plans. That may explain why Moore has recently been reminding people that he picked the two-year rate as he wrote his first article on it in the mid-1960s.

But Samsung seeks to break with convention, by upping the rate for flash memories, at least, to a doubling every year. And, roughly every autumn, the company has produced an example of a chip that could store twice as much as the last. So far, so good.

Samsung's relentless push looks as though it is coming at a cost.

There are three ways to squeeze more onto one chip. The first is the one that most companies promote - make the features smaller. However, you can only get so far with that approach. That is because the gap between successive manufacturing processes for memories only gives you a 25 to 30 per cent improvement in density.

Any further gains have to come from elsewhere. One is 'circuit cleverness' as Moore called it in the first expansion (and subtle revision) of Moore's Law, made in the mid-1970s. This happens in two ways with flash memories. One is just better design, gradually improving the design so that the memory cells pack together more efficiently. The other was the move to multi-level cells early - storing two bits per memory cell instead of one. However, this is pretty much a one-off boost as, to store four bits, the circuits in the memory device need to be able to distinguish between not two or four different levels but 16. That is going to be tough.

What do you have left? The size of the chip itself. In this way, what Samsung is doing with flash now mirrors what the Korean companies did with the dynamic memories (DRAMs) used in PCs in the late-1990s. To demonstrate their ability to keep winding up the capacity, they made the chips bigger and bigger. By 2001, Samsung had a 4Gbit DRAM but it was so big that it could never go into volume production. A market for 4Gbit DRAMs has yet to appear: current devices top out at 2Gbit and will not be mainstream for some years to come.

We seem to be seeing the same pattern with Samsung's flash now. To keep up with Hwang's projection, the company's designers seem to be cranking up the die size. It's been a few years since Samsung disclosed the cell size of its largest flash memories but the company has provided a few clues - mostly recently in picture form – and tend to back up some quick calculations.

Why is this important? Die size is one of the most important determinants of manufacturing cost. Up to about 150sq mm, the cost is not too bad. However, the memories you are most likely to buy in bulk tend to be somewhere between 70 and 100sq mm. But, according to my calculations, the size of the 32Gbit chip that Samsung pulled out of the hat last year was heading into the 250 to 280sq mm range. The latest one, doubling again to 64Gb, looks to be as big as 450sq mm. The Korean giant is not going to be cranking those out the way it can with its current cash cows in the 8 and 16Gbit range. What is more likely is that Samsung will use the process developed for the 64Gb memory to make cheaper 8, 16 and 32Gb devices come 2009 when this process is meant to into volume production. The 64Gbit will be for specialty users only - hard drive replacements in servers and the like - if the company ships any at all based on that process.

The question is what will happen next year when the designers have to pull another rabbit out of the hat to satisfy Hwang's Law. Such a device is likely to be very similar in size to the company's 2001 version of a 4Gbit DRAM, clocking it at something like 500sq mm assuming the standard scaling rules apply. However, the company's technologists are talking about moving into the third dimension and not just with chip stacks - the aim is to plonk the memory cells on top of each other on the same die. It is something that Toshiba claimed it had done earlier this year - there will be more about this when the IEDM conference rolls round in December. So, there is a chance Hwang's Law won't run out of steam before 2010 in terms of volume manufacture. But the cost and density trends are no longer moving in the same direction.


Samsung's development of the first 64G nand flash memory will serve as just another step to fully establishing the Hwang's Law. So far, judging from their achievements and current workings, it seems likely that the law will stay.

Samsung's development of the first 64G nand flash memory will serve as just another step to fully establishing the Hwang's Law. So far, judging from their achievements and current workings, it seems likely that the law will stay.