Sometimes, small deals can wind up changing the shape of a market. The deal between Blaze DFM and TSMC that has been gestating for close to a year is possibly one of them: it recalls the giant leap of faith that Artisan took when it came up with the "free library" idea.
Basically, Blaze and TSMC have cut a deal that will see the Taiwanese foundry use a version of the Blaze MO tool to alter transistors in a layout to make them less leaky just prior to manufacturing. The idea is not new and fairly simple: you make the transistor gate longer on logic paths that don't need to be fast. This typically shifts the threshold voltage up, which cuts leakage. STMicroelectronics has been offering the same sort of modifications using different logic cells. What is different is the nature of the deal between Blaze and TSMC and what it could mean for the whole DFM business.
Instead of trying to sell tools on a per-seat basis for something like a couple of hundred thousand dollars – the regular EDA business model – TSMC will host the tool. Although the companies will not talk about the money side of the deal, it does look broadly similar to the Artisan free-library model, where the foundry paid a royalty to Artisan for each chip made and charged a bit more for each chip to the customer.
For Jacob Jacobsson, CEO of Blaze DFM, this approach, in a way, opens up money that isn't available to the EDA tools vendors. "EDA has a had a more or less stagnant $3bn budget for as long as we can remember. It is more attractive for us to align with the manufacturing side of the business."
As Artisan found with the cell-libraries business, customers seemed happier to put a little bit more on the money paid to the foundry to make each chip than cough up for a large initial licensing fee. People argue whether Artisan's move was good for the libraries business, but it worked pretty well for Artisan, which ended up being bought by ARM. And it worked for TSMC.
Similar to the original free-library deal, Blaze's deal with TSMC is exclusive. Asked whether the company might look at deals with other foundries along similar lines, Jacobsson said it's far more likely it will concentrate on TSMC, because the foundry has such a dominant position in the market.
The changes to the design are applied during optical proximity correction (OPC). These are subtle changes to the layout that improve the chances of the drawn feature turning up on the die. Jacobsson claimed that applying the modifications during the OPC phase allows more aggressive optimisations: the tool can be more confident that a change will result in a transistor with a gate of a given length than if the alterations were applied to the original GDS II layout file. OPC is also a process that TSMC controls, so it's able to fold things like this into the flow quite easily.
Jacobsson said there is plenty of potential to push DFM into the foundry. The company's founder, Professor Andrew Kahng of the University of California at San Diego, has talked about the types of changes that are possible at conferences such as ESSCIRC. This deal does go some way to explain a rather opaque statement of Kahng's during the September conference in Munich. Talking about the guard bands applied to cell libraries to prevent designs failing due to vagaries in the manufacturing process, he said: "If you take canonical, TSMC-style libraries, you can see that some guard-band reduction results in higher yield because the die is smaller. There are some interesting trade-offs that are possible if you play with motivation. Dare I suggest to the foundries that they could provide some incentives for reducing guard bands?"
And there are other places where OPC-stage modifications would come in handy - "opportunistic, do no harm OPC", as Kahng termed it. These are things like dummy poly - effectively strips of polysilicon laid down between actual transistor gates to improve manufacturability. Intel's already doing this kind of thing big-style on the lower metal layers in Penyrn, as Chipworks has found.
Now, no-one is going to switch to TSMC just because the company can apply a bit of leakage reduction - although it is clearly an additional selling point. But, the idea that DFM analysis performed at the foundry using tools from a company such as Blaze DFM might result in smaller or faster integrated circuits, that stacks even more of the chips in TSMC favour. As it it didn't have enough already.
Now, I don't know if Mike Fister is a chair-kicking kind of person. But if he is, I imagine one or two are looking a bit worse for wear right now. This kind of arrangement, which breaks from the old per-seat pricing model is just the kind of thing the Cadence chief has been talking about since he joined the number-one EDA company. More deals like this would lock companies such as Cadence out of entire chunks of the DFM business as only the biggest fabless chipmakers are going to want to pay upfront instead of seeing that cost absorbed into that of the devices made by their foundry.