TSMC's 5nm difference

21 April 2008

There was a telling moment in the conference call hosted by Altera ostensibly to talk about its 1Q08 results but also drop in a few hints about an upcoming family of programmable logic chips.

Historically, Altera and market leader Xilinx have taken lumps out of each other as they vied to be first onto each manufacturing process. But something changed at the 65nm process node. Xilinx was quick to get its high-end parts out on the 65nm technology, but nowhere near as quick as the company's claims over having first silicon on that process. Altera was behind but took the opposite tack: putting its cheaper Cyclones onto TSMC's 65nm process first. Then it all went quiet. The launch of the 45nm process went off with both Altera and Xilinx being uncharacteristically quiet. It began to look as though a kind of chip that had become the foundries' banker for early silicon had suddenly fallen off Moore's Law.

It seems that the programmable-logic makers are still in the running, just not as quick to jump on a new process as they used to be. And it seems that Altera wasn't aware just how advanced its next process would be until TSMC decided it would lop another 5nm off - in name at least.

At 32 minutes into the call, Altera CEO John Daane corrected financial analyst Uche Orji about the next generation: "Our 40nm, and it is 40 not 45...we did call it 45 earlier but only because TSMC had not announced that it was really 40. They did that a few weeks ago, so I can tell you that we are the lead customer on the 40nm process technology...both software as well as components will be shipped this year."

Got that? Up until a few weeks ago, Altera thought it was working on a 45nm process. Until someone at TSMC decided that they were better off calling it a 40nm process. It's no big surprise, because the people talking about the self-same process at the International Electron Device Meeting (IEDM) last December also thought of it as a 45nm process. Which kind of makes you wonder just what TSMC claimed to be shipping last autumn when the company said it had shipped 45nm-process wafers to lead customers.

The issue of what constitutes a process node is something that has exercised Kevin Gibb of Chipworks, the Canadian electronics-analysis company. The number we have been using to describe a process node has pretty much lost all meaning. I have to agree with him, as well as Kaizad Mistry of Intel, who said in his talk about Intel's 45nm process at IEDM: "Contacted gate pitch is perhaps the most important [design] rule for density.”

Once upon a time, the number associated with a given process meant how long the transistor gate was. Then, thanks to some optical trickery, everybody worked out that they could reduce the size of the gate, and increase the speed of circuits, by much more than traditional scaling rules. The result was that, by the time the industry hit 90nm, gates were down to less than 60nm in length. At 65nm, you could find devices with gates not much longer than 40nm.

Then, because leakage power was going through the roof, manufacturers slammed the brakes on. Intel's latest devices seem to have gates no shorter than their 65nm predecessors, at around 40nm. TSMC's '40nm' process looks to be in the same ballpark. The company showed a picture of a 30nm p-channel device. However, these tend to be shorter than the n-channel transistors that people tend to base the overall measurement on. Certainly, in the case of both Intel's and TSMC's processes, leakage from n-channel transistors picks up steam from about 38nm down.

If you look at contacted gate pitch - this basically determines how tightly you can pack transistors that you have actually wired up to circuits - there is hardly any difference between Intel's 45nm process and what TSMC claims to be its 40nm process. That comes in at 160nm, with TSMC being very slightly wider at 162nm.

So, what we have now is the situation where the chipmakers are going to quote numbers in the hope that everyone thinks, because they chose a smaller number in the press release, they are in the lead. It's reminiscent of the situation in the late 1990s when LSI Logic thought it was clever to quote a different measurement to the one everyone was using at the time to make out it was one generation ahead. You would have to spend ten or fifteen minutes going through what their claim even meant before getting on with the important stuff. It seems we are going to be back to those days now as Altera and Xilinx limber up for the next round.

Altera will no doubt declare that it is in the lead with a '40nm' process. It's not clear whether Xilinx will follow suit - we will have to wait and see. I'm still wondering what we should really call TSMC's first 45nm process, which, according to the foundry has dimensions around 10 per cent larger than what it calls '40nm'. If we assume that Intel's published process is more or less dead centre in the 45nm zone, that would make TSMC's older '45nm' process something like a 50nm.


what crap. The point of referring to this as 45nm was to at least attempt to maintain some degree of competitive advantage. Maybe you need to spend some time reading marketing for 10 years olds. Do you really think people get confused when investing billions in a new process. How sad.

Odd that RV740 based on TMSC's "40nm" tech has twice the transistor density of Nehalem on Intel's "45nm" tech.