Slugging it out at 28nm - whatever 28nm means

30 September 2008

If it seems like only yesterday that chipmakers were pumping up 45nm processes, it was. But this is now and the talk is about the next generation and the next generation and a half after that. There used to be some breathing space between semiconductor processes: about three years or so. Now that time has shrunk to two years, largely because all the other tricks used to reduce the size of transistors on chips have run out of steam.

So, just months after 45nm processes started to ramp, companies are now touting the 32nm process and its little brother, 28nm. Curiously, a bunch of them picked the same week to do it. How odd. TSMC has decided that 32nm is a process for wusses and that the action is going to be 10 per cent smaller at the 28nm node. The Common Platform gang, who have a conference today in Santa Clara to talk about it, are concentrating mainly on 32nm, but say they will have 28nm ready about the same time as TSMC.

In some respects, you can look at the Common Platform and TSMC moves as signifying a bit of a slip in the TSMC deadline. At first, TSMC was not going to follow Intel and introduce a process that used high-k dielectrics and metal gates instead of the silicon and silicon oxide-based gates that have served the industry faithfully for 40 years. At the International Electron Device Meeting (IEDM) last year, IBM began to talk up high-k, metal-gate processes as well: expecting to introduce it at 32nm, in contrast to Intel's relatively early move at the 45nm node.

Then, earlier this year, TSMC told customers that it would offer both conventional silicon gates and the metal versions in parallel processes at 32nm. This has since mutated into metal gates at 28nm. Or, as history seems to be repeating itself, the process formerly known as 32nm has had a bit of a rebadging. Similar to the situation last year, when a process presented at IEDM as 45nm suddenly morphed into a 40nm offering, TSMC has a paper all about metal gates on - wait for it - 32nm when, apparently, it has no such process in development. The commercial 32nm process, which only has silicon gates, has been shoved into the shadows and emerge meekly later on next year. TSMC wants to shine the spotlight on 28nm.

Is TSMC's 28nm really a 32nm process? Frankly, it's anybody's guess right now. The company will not release details of the two things that would indicate whether it will really have a process that allows for smaller transistors than what IBM and the Common Platform gang plan. Those measurements are the contacted gate pitch - this tells you how far apart you can space transistors, so is a good marker for density - and the minimum SRAM cell size. However, if these numbers were good, I would expect TSMC to be shouting them from the rooftops.

Instead, what TSMC has done is shown how nervous it is about Common Platform even though its sales of foundry silicon dwarf those even of the Common Platform companies combined. Chartered Semiconductor Manufacturing is the third-placed foundry, but lies some way behind TSMC and UMC. IBM's foundry sales have slipped since 2005, according to IC Insights. Samsung, although the number-two chipmaker, has tiny foundry sales. Then again, it only got started a couple of years ago but has grown to be a top-ten foundry.

At 32nm, Common Platform has placed a big bet: that metal gates are not only good for high-end processors - this is why Intel jumped early - but for low-power, mobile devices. The deal that the companies tied up with ARM was all about pushing into the nascent market for mobile Internet devices. Buoyed up by bullish projections over growth in this area, the Common Platform people reckon they have a very strong position.

The reason why is that, although metal gates potentially push up cost, you can make some trade-offs between power and speed. You can design a slower circuit and get a big drop in power. TSMC's foil to this is to push the silicon-gate process, claiming that if you run it a bit slower still, you can undercut the power consumption of a metal-gate process. What you do, in effect, is make the gate longer so that it switches more slowly and leaks less juice.

TSMC's claim that the power advantage of a silicon gate is inherent to the process on the basis that the conventional design suffers fewer parasitic effects in a low-power process. Although there is some truth to this, if you are willing to slow the circuit down to the right point, it ignores the fact that you have other options with a metal-gate process. TSMC's argument is somewhat undermined by its use of a graph that contains entirely arbitrary units on both axes that compares what it does to what IBM has claimed. It's not even clear how TSMC computed the values reported for the IBM 32nm process as they have seem to have been derived from a couple of graphs in a VLSI Technology Symposium paper.

tsmcsion.jpg

Yay, arbitrary units'r'us. Is this operating power, leakage power or some synthesis of both? How is performance measured? You decide. However, notice that the speed of the TSMC silicon-gate process is lower than that of the IBM one.

The problem for TSMC is that companies are now so worried about power consumption - just look at the problems of the iPhone 3G - they are more likely to go for something that gives them low power and decent speed than what they used to pick: low power and low cost. TSMC majors on the latter and says it will have the former soon. IBM is promising potential customers the low power and speed option, plus underlining the idea that there is more than one source for it. With the larger fabless and fab-light chipmakers the phrase "not single-sourced" has a reassuring ring to it. TSMC tries to get around this by operating parallel fab lines: but it is still the same company.

Although TSMC currently dominates 65nm foundry production, there is potential for the situation to swing round dramatically based on which process works for the bigger fabless chipmakers at 32nm. And it provides the best explanation for why the world's biggest foundry was keen to tout a sub-32nm process one day ahead of a seminar run by the competition.